1. Field of the Invention
The present invention relates to the fabrication of semiconductor devices with self-aligned, raised source/drain.
2. Discussion of Related Art
The self-aligned contact (SAC) is widely known as a fabrication technique for reducing the cell size of memory units. Memory devices fabricated using SACs are commonly formed on the same CMOS chip as the logic circuits that address them.
Higher logic circuit performance is often obtained by using salicide (self-aligned silicide) processes. Anneal of a refractory metal layer causes the underlying silicon to react with the metal layer and produces a silicide overlying gate electrode and source and drain regions. These silicided regions have lower resistance than non-silicided regions. This is especially true of smaller geometries.
Silicidation is widely used in the art. As device design density shrinks for CMOS devices covering both deep trench dynamic random access memory (DT DRAM) and addressing logic, existing process integration schemes fail to meet contact requirements, especially as CMOS devices are scaled down to 150 nm node. Success of future CMOS process integration will largely depend on successful formation of healthy contacts that provide ultra-shallow contact junctions (XJC) with low leakage and that also provide low contact resistance (RC)and with high doping concentration in the silicide contact interface (NC). Process integration also requires consideration of other critical process criteria such as cost, thermal budget, device impact, reliability, etc. However, there is presently no universal proposal to make an advanced contact meeting ultimate requirements due to complex interrelationships among these parameters, each having its own process integration steps.
Thus, there is a need for an integration scheme for formation of an advanced contact having characteristics of low RC, high NC, and shallow (XJC), all of which are all essential for CMOS devices scaled down to sub-150-nm node. The present invention provides such an integration scheme that works for W/WN gate electrodes, Dual Work Function Gates, Dual Gate MOSFETs, and SOI devices, among others.
The integration scheme of the present invention enables the formation of contacts meeting these fundamental requirements (as discussed above) for CMOS devices covering both DT DRAM and logic. This scheme integrates formation of self-aligned raised contact window structures with a W-Salicide combined with an ion mixing implantation method. This method comprises the steps of:
1. forming conventional junctions;
2. performing an integrated bit line contact/source contact (CB/CS) etch;
3. performing surface amortization;
4. growing hemispherical grain/meta-stable poly (HSG/MSP) selectively; it should be noted that HSG and MSP can be interchangeably used.
5. depositing W selectively;
6. performing ion mixing;
7. annealing junction;
8. performing a dedicated contact to gate (CG) etch; and
9. performing a metal line and local tier process.
This integration scheme results in shallow junctions with low contact resistance for deep-sub-150 nm devices.
The present invention provides a method of integrating self-aligned raised contact processes with a W-Salicide combined with an ion mixing implantation method to render junctions with low contact resistance (RC) that are ultra-shallow XJC and have high doping concentration in the interface (Nc).